Modern microprocessor designs are severely limited by wire delays within the chip. Like walking from one end of a building to the other, sending signals across a chip requires time and energy. Beyond a certain size, architects of buildings construct additional floors which can help reduce the distances traversed by the occupants. In a similar fashion, microprocessors of the future will be composed of multiple layers of circuitry arranged in a three-dimensional stack. This technology has the potential to significantly reduce the lengths of wires throughout the chip which can lead to an increase in performance with a simultaneous reduction in power consumption. The development of skyscrapers required the invention of new building architectures; likewise the 3D microprocessors of tomorrow will need new computer architectures to fully exploit this new technology. This project will research the impact of 3D integration technology on conventional single-core and multi-core processors as well as emergent "many-core" processors (many 10's or even 100's of cores on a chip). From these studies, new architectures specifically targeting a 3D technology will be developed. They key research challenges include answering how to best design the new architectures to extract performance and power benefits from the technology, how to cope with potential thermal problems that may arise from stacking multiple layers of highly active circuits, and how to build a compelling system using stacks of different types of devices (e.g., RF/analog, DRAM, flash, CMOS).
