The memory hierarchy of modern digital systems is quickly becoming the preeminent determinant of their performance, efficiency, reliability, and cost. The amount of memory integrated on-die in systems-on-chip and microprocessors has grown significantly and will likely dominate the die area in future generations. Trends in computer architecture are increasing the number and type of requestors making demands on the memory system, yet trends in IC manufacturing and process scaling are making the design and manufacture of efficient, robust memories more difficult. To address these trends, this project explores adding reconfigurability to the memory system at the circuit, microarchitecture, and architecture levels to boost the efficiency and robustness of the design. It also explores how reconfigurability can also be used to enhance the security of the design by obscuring the design intention and enabling efficient encryption implementations with a customized memory system. The conditions under which the increase in efficiency and security from tailoring the memory system to the application via reconfigurability outweighs the VLSI overheads of adding that reconfigurability will be investigated. How reconfigurability can be used to increase the robustness and yield of digital ICs by allowing the memory to adapt to process, voltage, and temperature variations and mask faults occurring at manufacture-time and after deployment will also be investigated. In summary, this project should result in reconfigurable memory solutions targeted at efficient, secure, robust, general-purpose computing systems and an understanding of the overall reconfigurable memory design space.
This project explored adding reconfigurability to the memory hierarchy of modern digital systems at the circuit, microarchitecture, and architecture levels to boost the efficiency and robustness of the design. It also explored how reconfigurability can also be used to enhance the security of the design by obscuring the design intention and enabling efficient encryption implementations with a customized memory system. The project has resulted in a number of innovations in the design of robust memory systems including multiple variation tolerant SRAM test chips, novel error correction coding (ECC) techniques for SRAM and Flash memory, and a SRAM failure modeling study. On the security side, we have investigated the design of secure memory, efficient memory-based encryption blocks, and physical unclonable functions. We designed a testchip to measure the vulnerability of SRAM and DRAM to memory remanence attacks and countermeasures. Further, we developed a high-speed implementation of the Advanced Encryption Standard that uses a novel ROM-based S-Box unit that can achieve higher performance, energy efficiency, and side-channel attack resistance than conventional designs. Finally, the project included examination of the design of physical unclonable functions (PUFs) based on SRAM cells and sense amplifiers. These designs achieve randomness and unqiueness comparable to other state of the art designs, but at much improved area, power, and delay as well as high reliability. The reliability of our designs is comparable to conventional PUFs that use significant amounts of ECC which has high VLSI overheads (area, power, delay). On the education side, we have revived an undergraduate capstone design class on the use of reconfigurable logic (commercial FPGAs) for digital system design. The course is intended for advanced juniors and seniors interested in digital system design. The class tasks students with the design of a video game system that requires graphics, sound, and user input. Student projects have included physics accelerators, graphics processing uinits, emulations of classic gaming consoles, and designs customized for a particular game. At the end of each semester the class is taught, students hold a public demonstration of their systems. The project has involved research work from three PhD students as well as multiple masters and undergraduate students. Some undergraduate students worked over the summers under the auspices of the NSF REU program. Additionally, we have interacted with multiple industrial partners (partly through PhD student summer internships) to effectively transfer some of the developed technology to industry.
