By 2020, when thickness of Silicon will be less than a stack of a few atoms, the Semiconductor Industry Association roadmap predicts that further scaling CMOS circuits will not be sustainable, and expects a transition from CMOS to one or more of the presently nascent nano technologies such as resonant tunneling diodes (RTD), carbon nanotube FETs (CNFET) and carbon nanowires. Further in the future are devices such as single electron transistors (SET), and quantum cellular automata (QCA). An important and distinctive characteristic of these post-CMOS nano technologies is that they make it possible to efficiently and naturally implement threshold logic (TL). While TL concepts have been known since the 1960s, there has been no comprehensive work on synthesis and optimization of large TL networks similar to what we have witnessed over the past 30 years for traditional CMOS logic gate networks.
This is a proposal to develop a comprehensive design methodology encompassing synthesis, optimization, verification, and testing of TL networks. We propose to investigate synthesis algorithms that start with a technology independent, functional description of the circuit. Optimization of TL networks poses unique problems. Regardless of the underlying technology, TL gates are realized by comparing the weighted sum of the inputs with a given threshold. This can be a comparison of voltages or currents. Since process variations can change the outcome of such a comparison, they not only effect the performance and power but can also change the function realized by the gate. We refer to this as the functional yield (FY). We will develop new algorithms that jointly maximize the FY, power consumption, and performance of a TL network over the space of process variables, e.g. device lengths, widths, threshold voltages, oxide thicknesses, etc. Methods for testing the manufactured circuit for functional correctness and delay using new parametric fault models will also be developed. Verifying the equivalence of a TL network to a given a functional specification has not yet been addressed. This is essential for verifying the result of the synthesis procedure as well as in determining the functional yield when the design parameters are represented as statistical quantities as models of process variations. Expected outcomes of this effort include: new CMOS and post-CMOS circuit architectures for TL gates; algorithms and tools to automatically synthesize, perform functional verification and generate test patterns for TL circuits; methods to compute the parametric yield of TL networks, modeling TL network parameters as correlated random variables; methods to perform joint optimization of functional yield, power consumption and performance of TL networks over the space of process variables.
Most integrated circuits are designed using CMOS. The project aimed at enabling design of threshold logic circuits so that they become mainstream technology. Threshold logic is a new paradigm for the design of logic circuits, and there is little design technology available at the present. A unified framework and CAD tools will eventually provide the same level of design automation for TL networks as is currently available for traditional logic networks. It is necessary that several challenges in synthesis and testing for manufacturing defects are resolved. This work provides solutions to a number of these challenges. The logic of a threshold gate for an input function is implemented by determining several weight values. A fast method to identify whether a function can be implemented as threshold has been introduced. It characterizes the function based on established correlations among the weight values. It is shown that the proposed method is capable to quickly characterize all functions that have less than eight inputs and has been shown to operate fast for functions with as many as forty inputs. Furthermore, comparisons with other existing heuristic methods show huge increase in the number of identified threshold functions, and drastic reduction in time and complexity. This project also introduced a new approach for determining weight values for a threshold logic function so that manufacturing defects can be tolerated as much as possible. A fault model for defects on weights forms the basis of an Automatic Test Pattern Generation tool that quickly determines whether the circuit has embedded threshold logic gates with weight-related defects. It has been shown that test patterns for stuck-at faults do not necessarily detect defects on weights, and a compaction tool has been presented to generate patterns that cover stuck-at faults as well as faults for weight-related defects. The proposed research activities will stimulate new directions by other researchers. They will help semiconductor companies produce more complex, more reliable, and more affordable electronic systems on a chip. This will benefit many industries and improve the quality of human life. This project is expected to enable further research activity in post-CMOS technology, especially in synthesis of reliable complex functional specifications.
