Future microprocessors will be multicore systems with significant real estate dedicated to on-chip cache memory. The potential performance of multicore processors far exceed that of traditional single-core processors, but their performance is limited by the memory system''s inability to deliver data to cores in a timely fashion. Traditional techniques for overcoming this memory bottleneck problem are power hungry, which makes them unsuitable for future power-limited designs. To overcome the memory bottleneck problem, we are evaluating a wide variety of multicore memory hierarchy design space options, with an eye towards both improving performance and decreasing power. Among the design options we are investigating are hierarchical versus tiled cache architectures, support for dynamic tile allocation policies, support for moving select computation to data, support for vector-style gather-scatter operations, support for selective updates, power-aware coherence protocols and prefetching mechanisms, and coherence and prefetching mechanisms that exploit heterogeneous wire technologies. Preliminary results indicate that these mechanisms will significantly increase performance and reduce power dissipation in future multicore processors.
