Collaborative Research: Applying Hardware-Inspired Methods for Multi- Core Software Design Brian C. Demsky University of California, Irvine
0725357 Collaborative Research: Applying Hardware-Inspired Methods for Multi- Core Software Design Michael B. Taylor University of California, San Diego
In the past, improvements in microprocessor capabilities were expressed largely through a combination of clock frequency increases and microarchitectural enhancements that were invisible to the typical developer. More recently, due to power and microarchitectural scalability issues, microprocessor designs have diverged from this path and have begun to focus on exposing improved semiconductor process capabilities through the multi-core abstraction, which integrates multiple independent processors into a single chip. The deployment of such explicitly-parallel multi-core processors has deep implications on the future of software systems. While parallel software has been largely unnecessary in desktop systems, it will become essential if we are to expect continued increases in software functionality and programmer productivity like those that society has enjoyed over the last 35 years.
This research investigates a new design methodology for developing the parallel software systems that are necessary to take advantage of multi-core processors. This methodology leverages concepts from hardware chip-design methodologies, which scale to millions of communicating parallel entities. This new design process enables the software developer to create flexible system designs that easily accommodate refinement of how the computation is realized. It does this by separating the functional design of the software system from the specification of how to organize the computation. To validate this new design methodology, the research project investigates the construction of synthesis and profiling tools that can be used to develop and refine these functional and organizational specifications. These specifications are in turn used to create an executable that is optimized for the specific multi-core microprocessor.
