Field programmable gate arrays (FPGAs) are capable of speedups ranging from the 10s to 1,000s over traditional general-purpose processors (CPUs) on frequently executed code segments. However, such speedups occur only when the capability of the FPGA is fully utilized. It is becoming increasingly apparent that the bandwidth into and out of the FPGA can quickly become a limiting factor in its utilization. It is possible to design and map a large circuit on an FPGA but not have the bandwidth to keep it busy. The proposed project explores techniques for partitioning code implemented either in hardware on FPGAs or as software running on CPUs of a multicore multiprocessor system that enable efficient use of parallel computing resources. Three specific models of CPU/FPGA acceleration are explored that span a wide range of computing platforms: from embedded systems at the low end to high-performance multiprocessor systems at the high end. These models, along with applications suitable for the intended platforms, are used to identify and quantify performance parameters of CPU/FPGA interaction that drive the proposed partitioning techniques. This exploratory research may pave they way for the design, implementation and evaluation of automated hardware/software partitioning techniques for CPU/FPGA multicore multiprocessor systems envisioned to be pervasive across the computing spectrum in the near future.
