The emergence of chip multiprocessors (CMPs) is ushering in a new era of high-performance on the desktop. Within several years, desktop computers could have tens to even hundreds of CPUs, leading to petascale performance. However, a problem looms on the horizon: current memory technology will not keep pace with the terabyte size and scales of future application data sets.
This project aims to overcome the obstacles of building a terabyte and beyond main memory. Our approach replaces a large main memory constructed with conventional DRAM with an even larger main memory constructed with phase-change memory (PCM). PCM has good scalability, exceptionally low power consumption, and no susceptibility to errors. To use PCM, there are several challenges, including relatively slow performance and poor write endurance. We will develop a new memory architecture, called Tera-PCM, to manage PCM acceess latency and to increase PCM longevity. Our hypothesis is that Tera-PCM can be used to construct a terabyte memory for desktop CMPs that is performance and endurance competitive with DRAM at a lower power cost. The project will impact both undergraduate and graduate students, through research opportunities and industry internships. Students from under-represented groups in computer science and computer engineering will be recruited to participate, furthering diversity.
