Quantum computers, if built, will have great impact on defense and commerce in the area of secure communication. They will also allow simulation of complex quantum systems, providing an important tool for nanotechnology. The principal challenge in actually building quantum computers is finding a way to tolerate imperfections. In fault-tolerant quantum computing (FTQC), the faulty operations that cause computational errors must be used to detect and correct those errors. A radical approach to FTQC is to base the computational scheme on topology. Computation is performed by braiding topological structures; fault-tolerance arises naturally due to the invariance of large-scale topology to small, local distortions caused by random errors. Until recently, implementation of this rather abstract idea has demanded exotic, unobserved physical particles or unrealistically high-dimensional structures. However, it was recently shown that topological FTQC may be achieved in a two-dimensional lattice of quantum bits in a scheme relying on a novel form of quantum entanglement called a cluster state.
This research investigates the conversion of topological cluster-state-based FTQC into a realistic, scalable, solid-state hardware architecture. The particular hardware studied relies critically on computation via communication, enabling reasonably sized quantum processors to be connected to form quantum communication networks or large quantum multicomputers. The investigators experimentally develop semiconductor-based quantum memories in optical microcavities, optimized for quantum logic mediated by light in integrated optical waveguides. The research includes the development of experimental methods to fabricate and characterize large arrays of these qubits, while detecting and compensating for fabrication defects. These experimental efforts are supported by theoretical development of scalable, topologically fault-tolerant architectures designed around the observed hardware limitations.
