Processors with tens or possibly hundreds of cores will be a reality within the next few years. To ensure that multi-core performance will scale with the increasing number of cores, innovative processor architectures are increasingly being deployed in hardware design. However, achieving the desired performance and efficiency on these large and complex architectures becomes a daunting task. This CAREER research project will construct new foundations for many-core scale architecture analysis, modeling and optimization, including: (1) informative and scalable methods to capture architectural characteristics across many-cores and hardware components; (2) fast and accurate predictive models to forecast the complex behavior of many-core architecture substrates with widely varied configuration parameters and execution conditions; (3) hardware and software mechanisms for efficient mining of architecture characteristics at large scales; and (4) global and cooperative resource and thermal management techniques for many-core architectures.
The scalability and sustainability of future many-core processors crucially depends on efficiently and intelligently managing an increasingly large and complex hardware investment. The novel resource management techniques and architecture/OS support will open the door for a new class of optimizations that cannot be effectively achieved using conventional methods. The integrated education and outreach plan will help the PI to educate a broad spectrum of citizens and students. This includes expanding computer architecture curriculum with new modeling and optimization techniques, interacting with teachers at minority-serving high-schools to boost students? interest in science and engineering, and collaborating with the computing industry to integrate the developed technologies into real-world processor design flow.
"This award is funded under the American Recovery and Reinvestment Act of 2009 (Public Law 111-5)."
