As silicon integrated circuit technology approaches its ultimate scaling and performance limits, we can expect a rapid proliferation of innovative proposals for fundamentally new information processing technologies. The quest for the first post-CMOS general purpose computing machines will likely emphasize digital computation in systems constructed from nanoscale building blocks. Proposals for new nanocomputing technologies will, however, be dificult to evaluate, both because nanocircuits are dificult to build and test experimentally and because phenomena that compromise the reliable physical representation and manipulation of information in nanoscale systems will pose new and unfamiliar challenges. These considerations motivate the development of new theoretical tools for assessing the fundamental physical limits to reliable processing of classical information in nanoscale systems, limits that follow from generic space, time and power constraints imposed by the technological objective of superseding silicon technology at the end of scaling.
This project aims to advance the fundamental physical description of digital information processing in (generally noisy and faulty) nanosystems and to develop approaches, built from such a description, that can be used to evaluate the ultimate information processing capabilities of proposed nanocomputing technologies. The first prototype assessment studies will emphasize two existing proposals---quantum-dot cellular automata and nanowire-based NASIC fabric implementations---and will integrate results from physical information theoretic analyses and physical circuit models. Other explorations will aim to provide technology-independent insights into issues of generic importance for nanocomputation, such as the physical costs of error correction. These investigations, taken together, will help to clarify the nature of fundamental physical limits in information processing and their practical consequences, which will become increasingly important as the quest for new nanocomputing technologies intensifies.
For the past half century, sustained advances in silicon integrated circuit technology enabled rapid evolution of computing and telecommunications and fueled economic growth. The ubiquitous "CMOS" transistor technology used in today’s silicon chips is, however, now operating near its inherent capacity, and further transistor miniaturization will likely compromise both performance and power efficiency. This unwelcome state of affairs has intensified the search for alternative chip technologies that may have the potential to one day supersede silicon CMOS, and innovative strategies for entirely new "post-CMOS" computing paradigms have been advanced. These strategies are based on new types of nanometer-scale building blocks instead of silicon transistors, and employ these nanostructures for computation in new and interesting ways. Many more such proposals can be expected as the pause in the historically reliable improvement of processor core performance unacceptably hinders progress in computing. Assessment of the ultimate prospects for new and unfamiliar nanocomputing technology proposals is, however, extremely challenging. New types of nanoscale devices and circuits are extraordinarily difficult to build and test experimentally, and "first demonstrations" from the laboratory – important and resource intensive as they are - reveal little about a technology’s ultimate capabilities. Computer models are also of limited use for evaluating ultimate limits. Highly refined computer simulations are routinely used to guide the development of silicon CMOS, but models of CMOS devices and circuits can continuously be validated and recalibrated by a vast and ever-expanding body of experimental data. The formulation and parameterization of models for not-yet existing technologies is, on the other hand, an uncertain endeavor at best. A new and unconventional ingredient is needed if we are to meaningfully navigate the post-CMOS computing landscape in the late CMOS era, particularly the far reaches of this landscape where the fundamental limits that bound the ultimate capabilities of various approaches are to be found. The above considerations suggest that we might best gauge what nature will and will not allow in post-CMOS nanocomputing by looking beyond the microscopic details of nanostructures and the current experimental state of the art. Crucial insights about the capabilities of various proposals should be accessible through direct physical description of the underlying computational strategies that they employ. Our approach is to seek such insights through fundamental physical description of the computational strategies employed by various paradigms, examination of the associated space, time and resource constraints imposed on the strategy by physical law, and consideration of the implications of these constraints for achieving the technological objective of superseding CMOS. In this project, we developed a general methodology for establishing ultimate performance limits and resource requirements for emerging nanocomputing paradigms. The methodology can be applied to concrete computing scenarios, defined by explicit circuit layouts and control schemes that are designed within a specified computing paradigm. The resulting bounds reflect fundamental physical limits associated with the computational strategy employed by the paradigm, as expressed in the circuit implementation. The validity of these bounds is underwritten by fundamental physical law - independent of the myriad assumptions, uncertain parameter estimates, and specification of structural details that are required for explicit device and circuit simulations – and they provide fundamental insights that are not available from simulations or experiments. We demonstrated application of our methodology in detailed illustrative studies of dynamic logic circuits designed within two proposed nanocomputing technology paradigms: quantum-dot cellular automata (QCA) and nano-application-specific-integrated-circuits (NASICs) based on crossed nanowires. Additional studies pursued as part of this work expanded the theoretical foundation of the methodology, addressed issues of generic importance for nanocomputing, and expanded the applicability of our approach beyond logic circuits. First steps were taken toward extension of our methodology to the study of minimum power dissipation in full processors. This nontrivial extension, fully realized, would enable comparative exploration of the energy costs unavoidably incurred at the architecture, circuit, and component levels in a wide variety of emerging nanoprocessor architectures. This project has advanced the physical description of computing processes and the understanding of associated fundamental limits relevant to nanocomputing, and has produced a methodology for assessing limits on the ultimate capabilities of new and unfamiliar nanocomputing technology proposals. Insights and results from this work were disseminated via journal articles and conference presentations, and engagement of the technical community was fostered through organization of specialized conference sessions and workshops. Graduate and undergraduate researchers participating directly in this project, and students exposed to its central concerns in the classroom, benefited from increased awareness of fundamental physical aspects of information processing and their practical consequences. Appreciation of these consequences will become increasingly valuable as the search for fundamentally new nanocomputing technologies intensifies.
