The trend towards multi-/many- core design has made network-on-chip (NoC) a crucial hardware component of future microprocessors. With the continuous down-scaling of CMOS processing technologies, reliability is becoming a primary target in NoC design. Negative Bias Temperature Instability (NBTI) is a critical reliability threat for deep sub-micrometer CMOS technologies. NBTI increases the PMOS transistor threshold voltage and reduces the drive current, causing failures in logic circuits and storage structures due to timing violations or minimum voltage limitations. Meanwhile, process variation (PV) - the divergence of transistor process parameters from their design specifications - caused by the difficulty in controlling sub-wavelength lithography and channel doping as CMOS manufacturing technology scales, results in variability in circuit performance/power and has become a major challenge in the design and fabrication of future microprocessors and NoCs. Since NBTI and PV affect both NoC delay and power, it is imperative to address these challenges at the NoC architecture design stage to ensure its efficiency as the underlying CMOS fabrication technologies continue to scale.
The goal of this project is to develop techniques for designing novel, cost-effective router microarchitectures and adaptive routing schemes that mitigate NBTI and PV impact on NoCs by leveraging the interplay between the two. The scalability and sustainability of future many-core processors crucially depend on the dependability of NoCs. Mechanisms that can simultaneously tolerate PV and NBTI will be investigated for enhancing the reliability of NoCs fabricated using nanoscale transistor technologies. The educational and outearch activities include recruiting graduate and undergraduate students from under-represented groups for this project and integration of research and education.
The trend towards multi-/many- core design has made network-on-chip (NoC) a crucial hardware component of future microprocessors. With the continuous down-scaling of CMOS processing technologies, reliability is becoming a primary target in NoC design. Several factors have converged to make Negative Bias Temperature Instability (NBTI) a critical reliability threat for deep sub-micrometer CMOS technologies. Meanwhile, process variation (PV) - the divergence of transistor process parameters from their design specifications - caused by the difficulty in controlling sub-wavelength lithography and channel doping as CMOS manufacturing technology scales, results in variability in circuit performance/power and has become a major challenge in the design and fabrication of future microprocessors and NoCs. Although PV and NBTI can be addressed at the device or circuit levels, such solutions are costly in terms of area and power and exhibit poor scalability. In NoC design, an ultra-low latency is desired since shared-memory workloads are highly sensitive to the interconnect latency. In addition, power management is also critical in a NoC. NoC design techniques that can effectively address the combined PV and NBTI effects are greatly needed. The goal of this project is to develop techniques for designing novel, cost-effective router microarchitectures and adaptive routing schemes that mitigate NBTI and PV impact on NoC by leveraging the benign interplay between the two. To be more specific, this research aims to develop hierarchical, process-variation-aware NBTI-tolerant NoC design techniques that achieve attractive trade-offs among performance, power, reliability and area overhead. To this end, we have performed the following investigations: (1) Developing PV-aware NBTI mitigation techniques; (2) Exploring static and dynamic PV-aware NBTI mitigation techniques for EVC-based NoC; (3) Tolerating thermal variation induced reliability issues in nano-photonic NoC design; and (4) ESPN: towards power-efficient and reliable NoC design for emerging technologies This research projects has produced 10 conference (MICRO-08, HPCA-09, MICRO-09, DSN-10, DSN-11, HPCA-11, ICCD-12, ISQED-13, HPCA-13, ISLPED-13) and 3 journal publications (IEEE Design & Test, TVLSI, and ACM JETC). The graduated students have traveled to the topic conferences to present their work to the research community. Four Ph.D. students and one Master students have participated into this project and have successfully defended their dissertation/thesis based on this research. Two of them received the prestigious CI fellowships. One of them received 2014 NSF CAREER Award. A high school student also participated in this research project. Via the REU supplementary grant, an undergraduate student was also involved.
