In future high-performance microprocessors, memory system organization and management is perhaps the most critical looming issue. Accesses to memory will incur long delays and energy overheads in various queuing structures and in long wires. Each access will experience non-uniform delay and energy overheads based on the location of the stored data. Efficient layout of data within the memory hierarchy is therefore essential for high performance and low power. In this proposal, the PIs put forth a comprehensive hardware/software strategy for data placement in cache/memory structures with non-uniform delay and power. Novel mechanisms are proposed to cost-effectively migrate pages within the memory hierarchy. These mechanisms will attempt to leverage hardware structures, OS support, compiler hints, and compiler transformations. The PIs also plan to engage in broader impact activities that encourage minority participation and augment research infrastructure.

Project Report

In modern computer systems, data is placed in various memory and cache modules. Each module has a different cost for access, in terms of both latency and energy. The goal of the project was to discover hardware and compiler techniques to place data in modules that would yield the lowest cost per access. In particular, in a multi-core system, it is important to place data in a module that is closest to the core that is performing the computation. The project resulted in eight peer-reviewed publications, three Ph.D. theses, and two Masters theses. A few of these publications focused on hardware/software techniques that used performance counters on a CPU chip and the operating system to estimate the optimal module for each page of data. Two of the papers design techniques that are implemented in the compiler. One of the papers focuses on hardware techniques to improve quality-of-service in different workloads in a datacenter. Finally, one of the papers introduces heterogeneity in the memory system and proposes a new data layout to exploit this heterogeneity. To increase the broader impact of this work, the PIs have released some of the tools used to carry out the project's evaluations. The project's infrastructure has been leveraged to improve graduate course offerings at Utah. The PIs have also been involved in several mentoring and community organization roles.

Agency
National Science Foundation (NSF)
Institute
Division of Computer and Communication Foundations (CCF)
Application #
0916436
Program Officer
Hong Jiang
Project Start
Project End
Budget Start
2009-09-01
Budget End
2013-08-31
Support Year
Fiscal Year
2009
Total Cost
$388,000
Indirect Cost
Name
University of Utah
Department
Type
DUNS #
City
Salt Lake City
State
UT
Country
United States
Zip Code
84112