Testing integrated circuits (ICs) requires storing large amounts of test data on a tester and transferring it to/from the chip-under-test. The bandwidth between the tester and chip is very limited due to limited pins and tester channels. Test data volume continues to grow dramatically with increasingly dense system-on-chips (SOCs) and three-dimensional ICs as well as the need for additional tests to target defects in nanometer designs. A major development in the field over the past decade has been the emergence of test compression technology which stores test data on the tester in compressed form and decompresses it on-chip. The commercialization of this technology has helped immensely in keeping up with rising test data volume. However, going forward, there is a need for a next generation of test compression technology that can provide significantly greater compression to handle the larger designs of the future. This research will develop new theory, concepts, and architectures that are fundamentally different from existing commercial technology and have the potential for providing an order of magnitude or more improvement for test stimulus compression as well as output response compaction.
Society increasingly relies on correct and dependable operation of electronic devices. The impact of this research will be to develop new technology to keep test costs down and make it economical to fit in more tests to improve product quality. This will be critical as the manufacturing process becomes increasingly difficult to control at smaller geometries. Participation of undergraduates, women, and minorities will be actively encouraged.
