Over recent decades, power and complexity challenges have limited the ability to derive continued growth in computing performance through clock frequency scaling. Future growth will come through implementing systems with many independent processors on the same chip. Challenges lie, however, in writing software for these systems, and in creating software that is portable across several hardware generations. For parallel software to smoothly exploit a chip's computation and communication capabilities, hardware needs better information regarding software's structure and resource requirements. Analogous to the traditional, fine-grained instruction set architecture (ISA), this research proposes a higher-level, coarse-grained System-level ISA or SISA. SISA provides information on computational chunks and the data or synchronization dependencies between them. Expressing software as a coarse-grained directed graph, SISA enables efficient, adaptive scheduling of parallel computation and communication. It also offers other benefits for reliability, energy-efficiency and portability.
The proposed research program will have broad impact in several ways. First, the PI has a solid track record of knowledge dissemination and technology transfer. This includes extensive collaborative relationships with industry, and several patents. In addition, the PI has a track record of releasing high-impact software tools for external use. The Wattch power modeling tool is one of five major tools distributions from her group, in use by thousands of computing researchers worldwide. The PI also has a strong track record of support for undergraduate research and underrepresented groups, and has also advised summers of undergraduate research with women and under-represented minorities through CRA-W and Princeton programs. She has been involved in teaching non-STEM students and multidisciplinary efforts, and will continue and broaden such activities through this research.
