"This award is funded under the American Recovery and Reinvestment Act of 2009 (Public Law 111-5)."
A fundamentally different approach for circuit design that has recently gaining popularity is sub-threshold circuits, where the power supply is set below the transistor threshold voltage to obtain energy savings when speed is not the primary constraint. Individual circuits or processing element designed at sub-threshold region operates slowly, but throughput of the circuit can be improved by operating many of them in parallel. Hence, a processing fabric with many sub-threshold cores can be a suitable platform for throughput-oriented parallel applications. This proposal explores the viability of 3D die-stacking of sub-threshold and super-threshold circuits for low power computing. More specifically, our sub-threshold die contains many small sub-threshold cores, whereas our super-threshold die consists of several large super-threshold cores. The sub-threshold cores are used as co-processors to execute massively parallel, high-throughput, low/mid-performance tasks at ultra low power, while the main super-threshold processors handle high-performance sequential tasks.
This new cooperative computing hardware is expected to provide a viable platform for many useful embedded software applications that require both high-performance/power tasks as well as low-performance/power tasks. 3D integration will allow each die to utilize the process technology optimized for sub- and super-threshold operation and be seamlessly integrated into a single system. TSV (through silicon via) based 3D communication requires no off-chip access, thereby reducing power consumption further. Sub-threshold circuits are currently used for some low-power applications such as watches, hearing aids, distributed sensor networks, filters, and even pipelined micro-processors. 3D integration is already available in the embedded domain, and the high-performance processor industry is actively evaluating this technology for general purpose computing. This research will fill a critical gap that is needed to make 3D-integrated sub-threshold multi-core co-processors a reality.
