Power consumption is an increasingly important issue across society. For communication, as the ranges of links in wireless networks continue to shrink, the power consumed in the encoding and decoding becomes a decidedly nontrivial factor in the choice of system architecture. This is particularly important in settings such as wireless patient monitoring, personal area networks, sensor networks, etc. Shannon's classical information theory only established the tradeoff between rate and transmit power as the probability of error goes to zero and the block-length goes to infinity. This research is about giving new conceptual tools for reasoning about the power consumption in encoding and decoding as well. The core idea is that in the age of billion transistor chips, the proper metric for complexity is the power consumed by the implementation.
Just as simplified channel models have enabled sophisticated analysis that has revealed deep insights into error correction and transmit power, this research develops simplified implementation models that are amenable to analysis. This reveals the fundamental tradeoffs underlying the interplay between transmission and processing powers. Crucially, the models developed are compatible with modern approaches to iterative and "turbo" decoding by massively parallel ASICs, while also not being limited to just the currently known families of sparse-graph codes. By developing a unified mathematical framework, this research allows us to understand the total power cost of meeting performance objectives like high rate, low distortion, low delay and low probability of error. This in turn leads to an understanding of how to better engineer wireless systems as a whole: opening up avenues for collaboration between circuit designers, communication theorists, and networking researchers working at higher layers.
