The semiconductor industry is at an interesting crossroads, where traditional scaling of CMOS devices is beginning to confront significant challenges that are threatening to derail the more than four-decades old Moore?s law. 3D integrated circuits (3D ICs) offer an exciting alternative, where in lieu of scaling, continuous increase in functionality, performance and integration density can be sustained indefinitely by stacking semiconductor layers on top of each other in a ?monolithic? manner. A 3D IC is comprised of two or more active (semiconducting) layers that have been thinned, bonded and interconnected using special vertical wires drilled through the active layers known as ?Through Silicon Vias (TSV)?. When TSVs (10-100 micrometer long) are used to replace the longest (several millimeters) on-chip horizontal wires as well as some chip-to-chip connections (on printed circuit boards), significant reduction in wire delay and chip power dissipation can be achieved. Moreover, 3D ICs also offer the most promising platform to implement ?More-than-Moore? technologies, bringing heterogeneous materials (Silicon, III-V semiconductors, Graphene, etc) and technologies (memory, logic, RF, mixed-signal, MEMS, optoelectronics, etc) on a single chip.
However, modeling and analysis of interconnects in 3D ICs present new and significantly more complex problems. In contrast with traditional interconnects, the modeling of high aspect-ratio TSVs embedded in a semiconducting material with non-uniform currents in the third dimension, and electromagnetic coupling of interconnects with multiple conductive substrates at high-frequencies, constitute new challenges for design and design-automation methods. Furthermore, the high power-density in 3D ICs due to multiple active layers and their limited heat removal options give rise to large three-dimensional thermal gradients, making it important to consider the coupling between thermal and electromagnetic properties of interconnects and the surrounding media. Finally, the need for accuracy is accompanied by the computational challenge of handling a large number of coupled interconnects at the system level, as 3D integration further exacerbates the size of the interconnect problem.
This project will develop the necessary foundations for coupled electrical-thermal modeling and analysis of interconnects and passives in 3D ICs, considering the electromagnetic coupling of general 3D interconnects with multiple substrates at ultra-high frequencies as well as the physical attributes of high aspect-ratio TSVs (including geometry, material and density), using thermally-aware and inherently efficient techniques to enable full-chip modeling of the large system of interconnects. The overall program also ties research to education at all levels besides focusing on recruitment and retention of underrepresented groups in nanoscience and engineering.
