The scaling of on-chip memory is tremendously challenged by the excessive amount of process variations and reliability degradation at the 22nm node and below. In current practice, full custom design and extensive experimentation on test silicon are often necessary to achieve the desired performance under all process, voltage, and temperature conditions. Although such an expensive approach is acceptable in today?s chip design, it drastically reduces design productivity and predictability. The situation becomes even more severe when the ever-increasing nature of variations narrows the design window and exacerbates memory design complexity. This proposal aims to develop innovative methodologies that will enable fast sign-off of on-chip memory at the end of the silicon roadmap and beyond, through the seamless integration of predictive variability models, statistical sampling schemes, robust optimization algorithms, and efficient silicon characterization techniques. Furthermore, these new outcomes will be integrated into an online framework to statistically benchmark post-Si memory design, helping illustrate the diverse opportunities of memory design beyond the 10nm node.
This research effort will facilitate fundamental research on reliable design with unreliable components, enhance design productivity for a wide range of applications, and expedite statistical design solution for emerging nanoelectronic devices. In addition, through novel education curricula and web-based dissemination tools, this project will transfer the newly developed design knowledge to a diverse population of students, who will lead the creation of future nanoscale integrated systems of all types, from computation, communication, to consumer electronics.
As semiconductor technology continues scaling to smaller feature sizes and complete system on-chip (SoC) design becomes a reality, on-chip memory, such as static random-access memory (SRAM), consumes an increasing percentage of chip area, comprising over 86% of the transistor count in server class microprocessors. Such a significant fraction of chip area occupied by memory circuit makes SRAM performance a major quality indicator of today’s complex integrated circuits. SRAM cells are often designed with smaller geometries than those in random logic. Therefore, various microscopic variations dramatically affect SRAM performance. The sensitivity to these atomistic fluctuations further escalates when low supply voltage is employed to reduce power consumption in many energy-constrained applications. This project has developed innovative methodologies that enable fast modeling and analysis of on-chip memory at the end of the silicon roadmap and beyond, through the seamless integration of predictive device models, statistical sampling schemes, robust optimization algorithms, and efficient silicon characterization techniques. In particular, the ASU team has developed compact modeling and characterization techniques of statistical fluctuations in SRAM cells, including both static process variations and temporal degradation effects. Based on fundamental physics, these models help assess the ultimate barriers to continual SRAM scaling. They serve as the cornerstone to fast statistical analysis of SRAM yield. Beyond the CMOS technology, the ASU team has developed SPICE models for emerging memory devices, particularly phase-change-memory and spin-transfer-torque based magnetic tunnel junction. The new models bridge the development of memory technologies and design exploration, helping illustrate the tremendous opportunities and possible limitations in future memory system. Furthermore, through novel education curricula and web-based dissemination tools, this project has successfully transferred the newly developed techniques to a diverse population of students, who will lead the creation of future nanoscale integrated systems of all types, from computation, communication, to consumer electronics. At ASU, compact modeling of variability and reliability has been integrated into a graduate-level course that is developed by the PI for educating the students on the latest developments in nanoscale CMOS design. The related knowledge is also disseminated through invited talks delivered by the PI at various conferences, as well as presentations at many semiconductor companies.
