Through-Silicon-Via (TSV) provides the possibility of arranging heterogeneous components across multiple dies at a fine level of granularity in 3D ICs. This can result in significant decrease in the overall wire length, delay, power, and form factor. Primarily due to their large size compared with other layout objects, however, TSVs cause significant non-uniform density distribution in various layers. This density issue is expected to cause trouble during chemical mechanical polishing (CMP) and require TSV-aware solutions. In addition, the CTE (coefficient of thermal expansion) mismatch between TSV copper and silicon causes significant thermal mechanical stress to the devices nearby during TSV manufacturing and circuit operation. This in turn affects the timing and power characteristics of the devices. The mechanical reliability of the substrate and devices are also affected by TSVs. However, little is known on what design tool and methodology changes are required to improve the manufacturability of TSV-based 3D ICs. This project would investigate three key DFM/DFR areas specific to 3D IC integration, namely, TSV-induced stress effect and its impact to the overall circuit timing and power, TSV impact to CMP and lithography, and TSV-induced reliability. Successful completion of the project would help us to gain in-depth understanding of manufacturability and reliability issues with 3D ICs and TSV technology and develop effective physical design solutions to overcome these issues. The proposal calls for a very strong collaboration between the researchers from the manufacturability and reliability modeling, simulation, and validation area and the researchers from circuit and physical design area for 3D ICs.
Through-Silicon-Via (TSV) provides the possibility of arranging heterogeneous components across multiple dies at a fine level of granularity in 3D ICs. This can result in significant decrease in the overall wire length, delay, power, and form factor. Primarily due to their large size compared with other layout objects, however, TSVs cause significant non-uniform density distribution in various layers. This density issue is expected to cause trouble during chemical mechanical polishing (CMP) and require TSV-aware solutions. In addition, the CTE (coefficient of thermal expansion) mismatch between TSV copper and silicon causes significant thermal mechanical stress to the devices nearby during TSV manufacturing and circuit operation. This in turn affects the timing and power characteristics of the devices. The mechanical reliability of substrate and devices are also affected by TSVs. Electro-migration (EM) continues to be a threat to signal and power delivery networks in 3D ICs, where mechanical stress and thermal hotspots exacerbate EM further. However, little is known on what design tool and methodology changes are required to improve the manufacturability of TSV-based 3D ICs. Throughout the project, we gained in-depth understanding of manufacturability and reliability issues with 3D ICs and TSV technology and developed effective physical design solutions to overcome these issues. We first learned that dies with high power density, if vertically stacked, heat-couple with each other and create local hotspots that are significantly hotter than the ones found in 2D ICs. This high temperature in turn exacerbates the long-term reliability of devices and wires in 3D ICs. Moreover, copper TSV expands and shrinks faster than silicon substrate during high temperature TSV fabrication steps, which leaves residual stress to the mechanical structure of a 3D IC. We found that this TSV-induced stress caused variations in device performance and pose concerns such as TSV de-lamination, cracks, etc. We studied how to model these complex phenomena, applied them to analyze the reliability of large-scale 3D circuits, and developed full-chip design methods to mitigate the issues. This project called for a very strong collaboration between the researchers from the manufacturability and reliability modeling, simulation, and validation area and the researchers from circuit and physical design area for 3D ICs. We believe that our research has generated a significant impact in the semiconductor industry. In particular, our research is featured as a monthly Research Highlight in the Communication of the ACM (CACM) in January 2014. CACM is the flagship publication of the Association for Computing Machinery (ACM), which is sent to all ACM members, currently numbering over 100,000. Two of our papers got nominated for the best paper award at the ACM Design Automation Conference in 2011 and 2012. Our accomplishments in TSV mechanical stress analysis and optimization include full-chip analysis [DAC’11], interfacial crack analysis [ICCAD’11], and chip/package co-analysis [DAC’12]. Our work on thermo-mechanical impact on device mobility includes full-chip STA [DAC’10] and variation-aware 3D placer [ICCAD’10]. Our work on electro-migration (EM) includes BEOL impact [ICCAD’11], EM-aware routing [ICCAD’12], TSV lifetime analysis [ICCAD’13], and multi-scale PDN EM analysis [ICCAD’13].
