As transistor count has increased exponentially with Moore?s Law, power has become the number one problem in microprocessor design. Traditional scaling theory relies on reducing supply voltages in proportion to the reduction in device dimensions to keep dynamic power in check. In addition, leakage power also increases exponentially with decreasing supply voltages. This project proposes a novel micro-architectural design technique whose goal is to avoid the power wall by migrating most of the functionality of a modern microprocessor to spin-torque transfer magneto-resistive random-access memory (STT-MRAM) ? a leakage resistant, non-volatile, resistive memory technology. The central idea is to implement most of the on-chip storage and combinational logic using scalable, leakage-resistant STT-MRAM arrays and lookup tables to lower power dissipation, thereby allowing many more active cores under a fixed power budget than a conventional implementation could afford. To accomplish this, the investigator addresses challenges all the way from the circuit-level implementation of fundamental hardware building blocks to the development of larger-scale micro-architectural resources, control policies, and management approaches. At the circuit level, the project explores the design of content-addressable memories, registers, hybrid cells, and lookup tables based on STT-MRAM. At the architecture level, novel cache architectures, latency-hiding techniques, throughput optimizations, and write-power mitigation mechanisms are employed throughout the memory hierarchy. Novel hybrid memory cells are explored to eliminate write throughput and latency problems in heavily written queues and register files, while adaptive write policies, loop stream detectors, and micro-architectural resource allocation mechanisms limit write power to a small fraction of what is possible under a naïve implementation. The project also addresses lookup-table based design of functional units and other combinational logic, as well as design- and run-time reconfiguration of these units.
Leveraging STT-MRAM in processor design holds the potential to induce a significant leap in the performance and scalability of computer systems, with tremendous positive fallout to science, technology, and society at large. The project is expected to pave the way towards efficient power-aware many-core processors that can scale to hundreds of active cores under a fixed power envelope. The educational component of the project involves (1) training both graduate and undergraduate students in computer architecture, (2) the introduction of a a new memory systems course that integrates resistive memories into the syllabus, and (3) an improved computer architecture curriculum that includes design experience for undergraduates. The investigator plans involvement in local outreach programs promoting the participation of women and underrepresented minorities in computer science and engineering, and initiating a new effort to increase the enrollment of minorities in University of Rochester's computer science and electrical and computer engineering programs.
