In a decade feature sizes of integrated circuits are expected to shrink from present day 45nm to 12nm, increasing soft error rates from once-per-year to once-per-day. The International Technology Roadmap for Semiconductors (ITRS) report recognizes reliability as one of the most important challenges for the next decade, and points out that soft errors are the primary threat. Soft errors are transient faults, caused mostly by cosmic radiations and can lead to incorrect results or total system failure. The impact of soft errors on terrestrial systems can be both dire and sweeping, with targets including financial systems, health-care databases, power-grid, and communication infrastructure. Although much work has been done towards protecting computing systems from soft errors, the need for even more power, performance and area-efficient schemes for protection against soft errors is undeniable.
This research builds upon existing hardware and microarchitectural schemes to provide even more power-efficient protection from soft errors, and will primarily be achieved by better application analysis. This research involves developing application analysis, and transforming the way application uses microarchitectural components to maximize protection from soft errors. Key components of this project are to: Develop analytical techniques to model vulnerability of i) L1 data cache, ii) register file, and iii) pipeline latches, and use the vulnerability estimates to drive compiler, microarchitectural, and hybrid techniques to provide power-efficient protection of the components. iv) Synergistically combine component-level protection to provide power-efficient, system-level protection. v) Develop techniques for dynamically trading off power and performance for reliability. vi) Develop schemes for power-efficient multi-core protection. Keeping computation reliable, and yet power, performance and cost efficient is crucial in maintaining the pace of technological advancement, securing national interests, and ultimately in improving the quality of life. PI plans to make public release of RP2Explore: a compiler-microarchitecture toolkit for quantitative study of power, performance, area, reliability, and thermal trade-offs in programmable platforms based on GCC for easy adaptability and maximal impact.
