This proposal addresses the grand challenge of reducing power consumption of digital electronic circuits leveraging off of a promising new automated design flow for asynchronous circuits. This novel flow actively manages data-flow within the circuit and is capable of disabling computational blocks that would otherwise perform unnecessary calculations and waste power. The proposed research is to develop mathematical software algorithms that will optimize the partitioning of the circuit into computational blocks to maximize the blocks that are disabled and thereby minimize power consumption.
The impact of this research will span engineering, scientific, and social values. First, it will enable synthesized asynchronous designs to be lower-power and faster and thus more compelling. Moreover, because the research is based on a formal framework of communicating processes it is generally applicable to many computational systems, including next-generation beyond-CMOS computational platforms. At the social level it will enable the enrichment of students at USC and other institutions as the tool flow is made more widely available. Lastly, it will provide a rich context for a pre-college outreach program in which the principal investigator teaches high-school students about the world of electrical engineering, integrated chip design, and in a greener economy and helping form a sustainable society
