This project examines the art and science of co-designing compilers and hardware for circuit-level timing speculation thereby enabling reliable, high-performance computer systems. Timing speculation, an exciting, forward-looking hardware design alternative, allows designers to abandon pessimistic design guidelines and consequently extract more performance from the silicon. Unfortunately, timing speculation has been under-served by contemporary compiler technologies. This research develops novel design paradigms that allow the compiler and architecture to be jointly optimized to build highly effective timing speculative systems, a significant industrial and societal benefit. Outreach efforts motivate students to pursue graduate study in computer science and engineering.
Given the promise of timing speculation but the prevailing downward focus of existing work, targeted code generation addresses neglected portions of the system stack and offers enticing possibilities. This research develops timing-aware compilation that applies instruction-level error rate models to analyze and optimize instruction sequences. By generating binaries specifically targeted for timing speculation, the compiler aims to significantly reduce incidence of timing errors which demand dynamic correction. This extends the reach of timing speculation by reducing recovery cost. This allows systems to operate at higher clock frequencies or enables better energy-efficiency through lower supply voltages. The research develops compact timing error rate models through machine learning techniques and determines how existing flow analysis present in modern compilers could be used to drive these error rate models. The compiler extends existing code optimizations to include the estimated impact of timing errors generated during analysis phases. The compiler technology is being used to examine new design paradigms for integrated timing speculative systems which include co-designed and co-optimized architectures and compilers.
