Precisely controlling the physical parameters of an integrated circuit (IC) fabrication process is becoming more challenging in advanced technology nodes. This lack of control manifests as increasing levels of variations in power and delay in product chips. Unfortunately, regional or within-die variations have increased sharply in recent technologies, and many are dependent on the context of the design layout region. The traditional methods of tracking process variations, e.g., those that utilize scribe line test structures, have become increasingly less effective for predicting power and delay variations within chips that they are adjacent to. This has driven the need for embedded test structures, i.e., those incorporated directly into the product IC. This research is designed to address the deficiencies in the current state-of-the-art of embedded test structure design by focusing on designs that are truly embedded and leverage as much of the existing chip infrastructure as possible. For example, power islands will be investigated as a means of obtaining regional leakage variations and non-invasive modifications to the scan chain architecture will be investigated as a means of measuring regional delay and power variations.
A key emphasis of the proposed work is to improve the correlation of embedded test structure measurements with actual chip parameters, e.g., by developing test and measurements techniques that are carried out under actual operating conditions. Both graduate and undergraduate students will participate in the design and test of fabricated chips, which will enhance their educational experience thus preparing them for a more technologically educated workforce for the IC industry.
