Heterogeneous multicores/Chip Multiprocessors (CMPs) are envisioned to be a key design paradigm to combat the challenges of power, memory, and reliability walls that are impeding chip design using deep sub-micron technology. There are so many dimensions to creating heterogeneous architectures, with the issues spanning multiple devices, technology platforms and software stacks. Further, despite the promise that heterogeneity offers, it is not clear (I) what are the most salient forms of heterogeneity that will be really needed, and (ii) how do all these forms interacting in non-intuitive ways at the entire system level. These issues make this topic a high-risk high-reward proposition. This project will provide preliminary results to gauge the potential and feasibility of heterogeneous architectures, and develop strategies for systematically evaluating them.
The semiconductor industry is vital to the national security and economy of the United States. With all major chip vendors projecting increased number of cores as the key to their future road maps, innovations in chip multiprocessors is critical. Enabling heterogeneous computing can largely reduce energy costs of computing, while making it more powerful and dependable. Collaboration with industry partners would facilitate direct transfer of many ideas to industry. The tools and techniques developed in this research will be made publicly available.
Multicore architectures or CMPs, consisting of several computing engines on a chip, have emerged as the most effective computing paradigm, which have made their way starting from supercomputers to mobile devices like cell phones. As such systems are expected to dominate the computing landscape in coming years, design of high performance and energy-efficient multicores has become a major research thrust. In this context, computer architects are exploring many avenues ranging from using new technologies to designing more efficient cores, memory systems and interconnects. It is expected that future multicores will embrace design heterogeneity by using emerging technologies such as non-volatile memory (NVM) and 3D packaging in designing such energy-efficient systems. However, the impact of such technologies on overall system performance and energy efficiency is an open area of research. The main goal of this one-year EAGER project is to explore cross-layer heterogeneity in designing energy-efficient multicore architectures (CMPs). Specifically, the objective is to examine the impact of emerging technologies in exploiting heterogeneity across the three main components of a CMP - computing cores, memory subsystem and on-chip interconnect. Heterogeneity in core design includes large and small cores, graphic processing units (GPUs), and domain specific accelerators. Memory heterogeneity includes design of cache and main memory with SRAM and emerging non-volatile memory (NVM) technologies and on-chip network design includes heterogeneity in router architectures, on-chip networks and 3D stacking. We have designed low-power TFET-based processors, heterogeneous architectures with CPUs and GPUs, NVM-based memory models and hybrid on-chip networks during the course of this project. Our initial results indicate that by exploiting heterogeneity in technology and design across processors, memory and on-chip networks, it is possible to achieve orders of magnitude improvement in performance and energy efficiency of real-world applications.
