This project seeks to improve the quality and reliability of Analog/Radio-Frequency (RF) integrated electronic circuits (ICs) by developing an intelligent system for systematically exploring the wealth of information generated throughout their production lifetime and applying it towards improving the effectiveness of their design, manufacturing, and testing. While a large amount of data is made available through extensive design simulations and measurements on actual fabricated circuits, there currently exists a striking lack of formal methods to efficiently extract meaningful information from this data. The research activities that will be carried out through this project aim to fill this void by developing correlation mining methods based on the most recent developments in the fields of machine learning and data mining. Ultimately, using data from actual IC productions provided by industrial partners (i.e. IBM and Texas Instruments), the objective of this project is to demonstrate the impact that such correlations can have on reducing the cost of testing, enhancing the yield of the production and enabling post-manufacturing calibration of analog/RF circuits.
This project will facilitate the cost-effective realization of robust electronic circuits and systems, thus enabling more reliable computing and promoting technology trustworthiness. The proposed research is complemented by educational and outreach activities, including the development of a new graduate-level course on applications of Machine-Learning in Computer Aided Design and Test and the involvement of graduate, undergraduate and high-school students in research with the groups of the Principal Investigators, the industrial partners, and the research laboratory of the international collaborator.
This project sought to develop an intelligent system for systematically exploring the wealth of information generated throughout the production lifetime of an analog/RF integrated circuit (IC) and applying it towards improving the effectiveness of its design, manufacturing, and testing. Accordingly, the key outcomes of this project include the following contributions: 1) A two-tier test system, which allows test engineers to explore the trade-off between test cost and test quality and, thereby, reduce the cost of analog/RF test. This two-tier system is based on correlation extraction, complemented with elaborate defect filtering and guard-banding methods, which result in specification test compaction of over 65% without sacrificing test quality. 2) A cost-effective, machine learning-based method for post-production performance calibration in tunable analog/RF circuits through the use of correlations and tunable knobs. This methods enables designed to become more aggressive in optimizing performances without having to worry about low yield, since the post-production calibration phase will tune the marginally failing devices and bring them back within their acceptable specification range. 3) A non-parametric density estimation method, which can be successfully employed to effectively learn the statistical distribution of performances from a small set of fabricated chip. These distributions can then be sampled to generate arbitrarily large synthetic samples, on which the merit figures of candidate tests can be evaluated. This capability has been demonstrated, with parts-per-million accuracy, thus facilitating an informed selection among various tests early in the process. 4) An open-source, integrated Model View Controller (MVC) framework to support sophisticated adaptive test analyses employing advanced statistical learning theory algorithms. This framework enables, early test metric estimation which provides reliable test metric estimates from very early in production from a small sample of devices. 5) A wafer-level spatial correlation identification methodology which creates interpolative models, enabling prediction of parameters spatially across a wafer. Using these models, e-test measurements (also known as inline or kerf measurements) which are collected on a few sampled dies on a wafer to monitor the health-of-line and to make wafer scrap decisions preceding final test, can now be estimated for the entire wafer. Similarly through these wafer-level interpolative models, final test for each die on the wafer can be estimated from a few sampled die, thereby reducing drastically the cost of test. 6) Training of two post-graduate and one undergraduate student on the cross-disciplinary subject of machine-learning applications in the area of robust semiconductor manufacturing and test. 7) Three journal papers and ten conference papers, along with numerous presentations at various venues, disseminating the findings of this project to the community. 8) Computer-Aided-Design software infrastructure and pertinent expertise, as well as a seminar introducing the topic to the community at the two institutions were the PI served as a faculty member during the duration of this project.
