As CMOS technologies scale down to smaller geometries, integrated circuits become more sensitive to aging-driven variations. Such variations can cause a manufactured part to become unreliable in the field over a period of time due to aging-induced circuit failures. To guard against this problem, it is essential to build design-time and run-time techniques that can model and optimize CMOS circuits. The AgELESS project brings together expertise in circuit design, computer-aided design, and test techniques, which together are expected to provide a more complete set of solutions to the overcome the reliability hurdle. This work explores several major aging-related failures, and develops a toolbox of techniques that can be used to enhance circuit reliability, while ensuring that the circuit meets all specifications on power/energy and performance. While AgELESS will not make a circuit ageless, it is expected to ensure that it will age less.
The techniques developed in this research will be applicable to a range of applications of interest to the semiconductor industry, including enterprise-class for high-end computing systems, mobile and wireless communication applications, and embedded electronics, and will be made available to industry through multiple avenues, including industrial collaborations and active dissemination of research results. The educational impact of this project will involve new course materials on reliability for the undergraduate and graduate curriculum, and will train future scientists/engineers to learn creative problem-solving skills.
