Advances in semiconductor technology in recent years allow billions of transistors to be integrated on the same chip, which makes power consumption the most critical design constraint. While the prevailing clocked synchronous logic has started to face more and more challenges as the transistor feature size continues to shrink, this research is to develop an innovative asynchronous digital processor design methodology and platform for energy efficiency, which provide a balanced power-speed tradeoff to deliver "just right" performance under all circumstances across a large variety of applications.
In our novel design methodology, given information for an application scenario and design constraints, appropriate asynchronous processing elements are selected and the number of cores in a parallel architecture is determined. This throughput analysis step is optimized by including a wide range of processing elements and by employing a fine-grained characterization process. During processor operation, the input data rate and the system utilization are monitored and compared with user preference to determine how many cores should remain active and also to adjust the supply voltage accordingly. A history-based forecasting mechanism is implemented for accurate yet efficient workload prediction.
Centralized and distributed voltage architectures for dynamic voltage scaling will be compared across wide dynamic ranges, along with the evaluation of various low voltage gate designs in facilitating extreme voltage scaling for power reduction. A series of prototype circuits will be designed, laid out, and simulated under various constraints and user settings. The results will be summarized and analyzed for performance evaluation and further optimization in the design methodology. Outcomes of this research have the potential to impact the battery-powered mobile computing and communication device industry, by enabling products that offer longer battery life, enhanced reliability, and reduced cost.
