The past decade has redefined the path of computer design in all aspects of computing. Whether the application is high-performance or general-purpose processors, the push is for improved performance through parallelism in the face of device constraints, bandwidth constraints, and power constraints. Area on chip is now "virtually free," while power and bandwidth are precious commodities. Recent research has proposed many approaches to tackling this problem, including heterogeneous architectures, specialized function units, reconfigurable cores and 3D-integration. However, this decade, computer designers must work within the design constraints wherein not all of the chip can be turned on simultaneously. Computer designers must find a way to classify programs by their architectural needs, and find the best configurations for each classification. This need, combined with the increased diversity in parallel algorithms, presents a challenge: finding "shapes" of computation that are meaningful both to the programmer and architect. It also presents the challenge of designing architectures for each computational classification.
This project will tackle this important problem by detecting algorithmic level parallel programming patterns, exploring a classification system using these patterns, and proposing computer features that are beneficial for each pattern. We will design a pattern-based dynamic architecture that includes pattern-specific hardware optimizations that are in turn enabled only when needed. For detection, we will investigate both programmer supplied inference detection as well as online dynamic detection.
This activity will promote teaching, training, and learning. It will be a goal of this project to involve the participation of underrepresented groups both through REU activities and through the selection of the graduate student involved in this project. The results of this research will be disseminated broadly via high-profile conference proceedings, scientific journals and via the Internet. Since we believe strongly that parallel patterns will drive computer design in the future, we propose developing PatternBench, a benchmark suite that encapsulates the space of all possible parallel patterns. Our plan is to make this benchmark suite available to aid in dissemination of this research. The broader impact to society of this work is to make future computers more power-efficient and to allow for continued performance scaling in the new era.
