Timing violations, an artifact of rapid technology scaling, embody a central reliability challenge in microprocessor design. A vast body of existing techniques in the landscape of timing violations fall under two broad categories: reactive and proactive. In both of these schemes, the lack of sufficient time in identifying an upcoming timing violation limits the scope of corrective techniques, incurring a large recovery overhead, or loss in fault coverage, respectively. Using a cross-layer analysis combining information from the application, architecture and circuit layers, this CAREER project demonstrates that timing violations can be predicted several clock cycles early. Early prediction of timing violations can offer a vast leverage in robust system design, opening up a promising direction for future systems research. In this paradigm, microprocessors can operate at a tighter frequency, where predictable errors frequently occur and are tolerated with minimal performance loss. Such a system design style can reshape physical design algorithms, boosting the energy efficient frontiers for microprocessor components.
Research in the nascent area of cross-layer design will enable circuit designers and system architects to increase collaborative design, and develop affordable, energy efficient and reliable computer systems. The rapid growth and evolution of integrated circuits creates a huge demand of Computer Engineering skill sets for addressing upcoming challenges. The CAREER project seeks to create a stream of future engineers capable of tackling growing unreliability in integrated circuits through focused knowledge dissemination. Undergraduates, women and minorities will be actively sought for participation through the existing platforms at Utah State University such as the Society of Women Engineers (SWE), Engineering State and Center for Women and Gender (CWG) programs.
