As transistors get smaller, they become increasingly susceptible to variations in their timing characteristics. One way to deal with possible variations is to assume worst-case characteristics during hardware design. Unfortunately, the power and performance costs of worst-case design are becoming prohibitive. Consequently, processor designers have sought more aggressive design styles that permit better-than-worst-case operation. One such approach uses "canary circuits" that indicate when a processor is on the verge of unsafe operation due to variations. This research investigates "software canaries" - software routines that exercise the most susceptible circuits of a processor to determine an aggressive safe operating point. Software canaries enable all the benefits of hardware canary circuits, without the corresponding hardware overhead. More importantly, they may provide additional benefits as they can track aging and temperature - variations that may be indistinguishable to hardware canary circuits. Furthermore, unlike hardware canary circuits, they allow identifying the most aggressive operating point on a per application basis. This research focuses on exploring the benefits of software canaries, developing use cases, developing techniques for building software canaries for different microarchitectures, and developing microarchitecture and system support needed to support software-canary-based execution.
The broader impact of the research lies in enabling computing systems with significantly lower energy consumption by selecting aggressive operating points. Other specific impacts include development of open source tools that may be used for further work by other research groups, and a greater discussion of variations and energy efficiency in graduate and undergraduate coursework.
