Circuit reliability, process variations, and environmental variations have become major challenges to address in advanced integrated circuit designs, especially for parts deployed in critical-life applications such as automotive, medical devices, aerospace, etc. The goal of this project is to develop novel and efficient test infrastructures, multi-level test approaches, and methods to eliminate wasteful guardband for improving performance and reliability of the circuit throughout its lifetime operation under any workload.
The intellectual merits include (1) design of new test and measurement infrastructure while targeting aging, minimum available slack, noise, and timing uncertainties in the circuit, (2) generation of test patterns considering different noise/workload conditions on target paths and selection of paths to be targeted for test and reliability analysis, (3) analyzing the measurement data at three different levels, namely manufacturing test and silicon validation, system bring up, and in-the-field test, and finally (4) analyzing data collected from a SOC design fabricated in an advanced technology node.
This project will lead to reduced design re-spin and shrinking gap between manufacturing test and system test, thereby lowering manufacturing cost. The results of this project will alleviate debugging and diagnosis problems. Resulting benefits for society include: (i) more reliable electronic systems for critical applications; (ii) cheaper and more dependable computing platforms; (iii) realization of the much sought-after goal of "zero defects" in the field for automotive, medical, and space applications. Students involved in this research will be prepared for the semiconductor industry workforce.
