New computing applications require dramatic increases in the energy efficiency of processors. These applications include personal health monitoring with wearable body sensors and data processing onboard tiny robotic rescue helicopters. Energy efficiency allows such applications to run on small batteries, thus achieving the necessary small form factor. Until recently, energy efficiency was achieved by shrinking transistors. While the Moore's Law still keeps shrinking transistors, the smaller transistors are no longer significantly more energy efficient than large ones. As a result, the quest for energy efficiency has shifted from transistor fabrication to designing software and hardware that work well together. Among key questions is how minimalistic can hardware be without affecting the productivity of programming that hardware. Minimalistic hardware would not burn energy on tasks that support programmability, so investigating how to compile programs for minimalistic hardware is of increased interest.
Traditionally, hardware complexity has been hidden under a programming model and a compiler. The less heroic the compiler, the more likely was the technology to succeed (c.f., CUDA's widespread adoption). Unfortunately, a simple compiler breaks down on hardware without programmability features such as caches. This proposal investigates extending the compiler with a synthesizer, which has the power to search a space of alternative programs. The design decision to rely on search frees the compiler writer from having to develop a (deterministic) compilation algorithm. As a case study, this project addresses the programmability question through a programming framework for a spatial ultra-low-power processor design. The framework includes a programming model and a synthesis-aided compiler tool chain. The programming model develops a solver-aided domain specific language (SDSL) that includes constructs for partitioning programs across processor cores. The SDLS is implemented on the Rosette framework for SDSL construction.