To sustain performance scaling with the continued progression of Moore?s Law in deep nanometer nodes, we must seek new and innovative advances in energy efficient computing architectures. Such advances are central to the effective operation of all modern processors in platforms ranging from mobile devices to data centers and high-performance computing (HPC) machines that drive national initiatives in key areas such as science, finance, and defense. The major determinants of power consumption are voltage and frequency. The continuing need to scale energy efficiency in the presence of time-varying application workloads increases the number of fine grained power states as well as the frequency of power state transitions in future processors. However, rapid and fine-grained power state transitions increases the time spent in power state transitions as a percentage of the execution time. Thus unchallenged, designers will soon be faced with an impossible choice between energy efficiency (increasing frequency of transitions) and performance loss (time spent in making transitions). However, sustaining performance scaling will need concurrent advances in both.
Transient architectures developed in this proposal aim to address this challenge. These are processor microarchitectures that can continue to perform useful computation during power state transitions. The challenges lay in the fact that during power state transitions the supply voltage received by a logic circuit is not stable for a finite duration. Conventionally, a synchronous digital circuit cannot operate correctly when the supply voltage is varying, making execution unreliable during this unstable period. The transient architectures aim to perform useful computation even under unstable supply during these power state transitions by employing a unique combination of innovative power regulation circuits, adaptive computational circuits, and processor microarchitecture technologies. The key concepts enable computational circuits to ramp up to full speed operation in concert with supply voltage transition thereby performing useful computation during power state transitions. The operational principles underlying transient architectures will be demonstrated via silicon test chips and micro-architectural simulations.
This departure from conventional thinking can transform the state of the practice in the design of power and energy efficient processor microarchitectures leading to new ultra-low power designs with superior energy-performance tradeoffs than the state of the practice.
