With increased levels of device integration accompanied by use of transistors with deep-nanometer feature sizes, analog, switched-capacitor and digital filters that are used for isolating "wanted" signals in electronic circuits from "unwanted" ones, have become increasingly susceptible to noise induced by the operation of vast amounts of circuitry. Such noise leads to degradation of signal quality and loss of Quality of Service (QoS) of the end application (wireless communication, sensing, etc). One way to address the noise issue is to devise a noise-cancellation scheme similar to that used in popular noise-canceling headphones. Such techniques are difficult to implement on-chip due to the unknown nature of on-chip noise sources. To solve this problem, we introduce limited redundancy into the filter implementation, that allows the filter to check for signals (injected noise) at internal circuit nodes that are inconsistent with the input signals to the filter and compensate for their effects on filter operation. As long as the injected noise is localized within sub-regions of the filter, near-perfect noise/error cancellation is achieved regardless of the source of the noise and the manner in which it couples to the filter involved.
As the demand for high speed wireless communications technology grows, there will be a strong need to develop research and education programs that produce personnel that can service the relevant system design, yield management and field maintenance problems in industry. Students working on this project will participate in summer internship programs with industry and work on real industry test cases. This will facilitate technology transfer to industry and will also challenge the academic researchers and students to address practical technology transfer issues that eventually lead to commercialization of the technology developed, thus impacting economy and society.
Technical details of the project involve design of analog, switched-capacitor and digital filters that are resilient to noise/errors induced by electrical bugs such as due to power/ground bounce and crosstalk. A key goal is to develop a design methodology that provides maximum resilience to noise induced errors with the least impact on area and power consumption. The project will result in a chip design for proof-of-concept and validation of the fundamental resilience concepts. The approach is based on the principle of checksum based encodings of the state transformation matrices of linear as well as linearized-nonlinear analog, switched-capacitor and digital filters. When noise is injected into a specific node of the filter, the filter encoding can be used to generate a phase-inverted version of the injected noise. By feeding the latter into the affected circuit state, perfect or near-perfect noise/error cancellation can be achieved. A key benefit of this approach is that it is independent of the source of the noise/error as long as the effect of the noise/error injection is localized to one or a few system states.
