Programming for and leveraging the benefits of scalable and highly parallel computer architectures is becoming increasingly challenging. In order to ease programmer and user effort in achieving efficient use of parallel architectures and to enable optimal usage of parallel hardware both within a single chip and across a data center, this project explores the co-design of a fine-grain configurable (down to the ALU, FPU, Cache bank, fetch unit, etc) architecture along with a software optimizing runtime system which controls the architecture's configuration. This runtime management system understands high-level goals and constraints such as optimizing for power, latency, cost, or complex mixed-goals and dynamically allocates fine-grain resources to meet the constraints. This project will evaluate and design a configurable manycore-inspired architecture and a self-adapting runtime system.
This project will investigate the creation of a complete, scalable, self-adaptive computing system; and will push the boundaries of adapting systems by utilizing hardware that is configurable and monitorable below the processor core level. By providing such a flexible and highly monitored architecture to the adaptation runtime, this project will explore the scalability of adaptive runtime algorithms to handle a game-changing increase in the number of controllable parameters. This project will explore the extent to which it is fruitful to configure a parallel architecture.
