Emerging applications in the growing domains of cloud, internet-of-things, and high-performance computing require higher levels of parallelism and much larger data transfers compared to applications of the past. In tandem, power and thermal constraints limit the number of transistors that can be used simultaneously on a chip and this limit has led to the ?Dark Silicon? problem. These difficulties in harnessing the full potential of computer chips exacerbate the challenge of building efficient high-performance systems. This project proposes to use 2.5D integration technology with silicon-photonic networks-on-chip (NOCs) to build heterogeneous computing systems that provide the desired parallelism, heterogeneity, and network bandwidth to handle the demands of the next-generation applications. A major outcome of the project will be a set of optimization methods that will enable efficient and robust design and operation of 2.5D systems with silicon-photonic NOCs. The project seeks to accelerate the design of high-performance, energy-efficient systems that are able to cater to growing bandwidth and performance needs and, in this way, enable a wider spectrum of cognitive data-intensive applications. Planned educational and outreach activities include the design of tutorials and workshops focused on training future engineers on cross-layer design problems, involvement of undergraduate, under-represented minority, and women students in various aspects of the research, and interactions with research centers and industry to accelerate technology transfer.
The research goal of the proposal is to design novel cross-layer design automation methods for 2.5D-integrated heterogeneous systems with silicon-photonic NOCs, and to quantitatively demonstrate the benefits of these 2.5D systems with respect to energy efficiency, robustness, and performance. The proposed work bridges the gap among device, physical design, architecture, and application layers when designing systems with silicon-photonic NOCs to dramatically improve system efficiency and robustness. Specific project thrusts include designing: (1) a modeling stack to quantify cross-layer interactions (from devices to applications) in a 2.5D system and inform optimizers to enable energy-efficient silicon-photonic NOC design and management; (2) design-time methods that orchestrate architecture design, chiplet placement, NOC design/routing, laser placement, and cooling design to maximize system performance under power and temperature constraints; (3) thermally-aware design/runtime optimization techniques that are aware of silicon-photonic device properties and their sensitivity to thermal variations; and (4) cross-layer optimization methods that help navigate a complex space of design choices and runtime knobs.
