When the supply voltage of a transistor drops, its power consumption reduces significantly but at the cost of delay increase. A scientific breakthrough found in 2008 named negative capacitance states that if a ferroelectric material is used for the gate of a transistor, its delay does not degrade even when the voltage reduces. This remarkable effect has a potential to offer very low power yet high performance electronic switches. Existing studies have demonstrated such benefits at individual transistor-level, but its impact on large-scale circuits and systems has not been well studied. The goal of the proposed research is to quantify these benefits first and then to develop ways to further the benefits. The project, by design, is interdisciplinary in nature and will cover a large range of topics from material science, device engineering to circuit design. The project is expected to provide a unique and interdisciplinary experience for the participating graduate and undergraduate students. The STEM outreach and education programs described will help high school and lower-level college students to seek further studies and careers in semiconductor science and engineering.
The team proposes a holistic approach to negative capacitance transistor technology that incorporates experimental research at the most fundamental material-device level, going all the way up to the full chip level circuit simulations. They will develop physics-based compact models for their experimental devices and use these experimentally calibrated models to investigate the performance of negative capacitance transistors corresponding to advance technology nodes such as 10 nm and 7 nm. These models will serve as the intermediary that will translate the results from the basic experiments for chip-level simulations. Large-scale full-chip designs targeting internet-of-things to high-performance applications will be built and optimized to maintain the device superiority all the way up to system and circuit-level. For negative capacitance technology to successfully resolve the power dissipation bottleneck in computing and spur new paradigms in electronics, disjoint research in each individual levels in the hierarchy will not bring about the necessary breakthroughs. The team will develop an approach where all aspects of physics, materials, devices, compact models and circuits are optimized in a self-consistent manner.
