This project addresses design challenges in building a brain-like computing system through three-dimensional (3D) neuromorphic circuits, and using Through Silicon Via (TSV) - based 3D Integrated Circuits. The approach is expected to reduce the design area occupied by conventional capacitors, resulting in chip design-area reduction and improvement in chip performance and efficiency. A Computer Aided Design framework will be developed to optimize the use of these reconfigured TSVs. The resulting devices, circuits, and framework will be validated using silicon tape outs and emerging applications, e.g., advanced wireless broadband communications. In addition to enabling educational and outreach programs, the project provides industrial experience for underrepresented students, thus contributing to the development of workforce in this area of technology.
The project undertakes a systematic attempt to explore the alternative use of TSVs as capacitors in 3D Neuromorphic Computing (NC) circuits. The NC chips require membrane capacitors to power the process of "neuron firing", and, depending on specifications, these capacitors can occupy from 25-75% of state-of-the-art electronic neuron's design area. This project entails the design of a NC chip in which idle TSVs are co-opted to function as capacitors. Three specific thrusts are proposed: reconfiguration and adaption of idle TSVs as capacitors; scalable, robust, and energy-efficient 3D NC circuit design; and system prototype and emerging applications.
This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.
