The need to scale computation capabilities without scaling up energy consumption is as high as ever. The one-size-fits-all computation model performs well on an average case but suffers in performance and energy efficiency for many individual applications. Customization plays a crucial role in processor design going forward. However, customization outside traditional programming and execution models has not yet fulfilled its promise. This project provides the hardware/software interface with diverse capabilities to enable the seamless adoption of heterogeneous hardware, without breaking traditional programming and execution models. This work enables new levels of specialization within the microarchitecture without disrupting the traditional general-purpose programming interface. The research team will continue increase and support workforce diversity within their department, continuing and broadening a new set of initiatives recently introduced.
This project explores novel, non-intrusive, and programmer-transparent compiler, runtime, and decoder techniques that will unlock several previously unexplored hardware designs that not only offer greater throughput and efficiency for multithreaded workloads, but substantially improve existing levels of single thread performance. This work introduces two novel architectures: (1) Composite-ISA (Instruction Set Architecture) Heterogeneous Multicores that can match the gains of multi-ISA heterogeneity using a single composite-ISA derived from a large superset x86-like ISA, and (2) Context-Sensitive Decoding that leverages the internal micro-op translation feature of the modern decoders to seamlessly morph and tailor execution to changing environmental conditions, without recompilation or binary translation, and at no significant performance overhead. This level of customization is especially useful in responding to new malware threats such as the Meltdown and Spectre vulnerabilities, which could otherwise require complete hardware redesign and/or incur prohibitively high performance costs due to software/OS-based mechanisms.
This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.
