As the density of components on a VLSI chip continues to grow, the need to develop computer-aided tools for custom chips is crucial for the continued advance of VLSI technology. This research concentrates on custom chip layout, an area in which major breakthrough is expected in the next decade. The aim here is to develop theoretical knowledge, efficient algorithms, and experimental layout systems. The long-term plan is to develop a goal-oriented, hierarchical, building block system (an automatic custom layout system for placement and routing in VLSI design) for custom VLSI chips. Logical design, simulation, and physical layout are run in parallel to reduce design time and produce error-free layout. Hierarchical simulators are to be integrated with a hierarchical building block layout system. System flexibility will allow designer's intervention.
