Prior research has resulted in the definition of a new associative processing system using a novel VLSI associative memory. The system, an associative parallel processor unit with multi-operand processing capability, behaves as a dynamically reconfigurable array of associative processors all performing the same function with different operands on disjoint data sets. A simulator for this proposed architecture has been built. This project focuses on the exploration and evaluation of different algorithms of importance in image processing mapped onto this architecture. The results of these simulation studies are expected to aid in the refinement of the architecture such that the resulting design will evolve into a fully parallel associative computer capable of solving a wide and important class of problems. A novel architecture is proposed. At this point in time an in-depth study of the architecture including the evaluation of important algorithms mapped onto this architecture will enhance our understanding of the significance of this new architecture.
