The availability of low-cost, high-density, high-speed processors and memories in VLSI, together with the increasing demands for high-performance in signal processing, has resulted in numerous proposals for highly parallel signal processing architectures. Since reliability is a key requirement, this research addresses the issues involved in the design of fault tolerance features in these parallel architectures. The specific, unique and promising approach to fault tolerance in this project is the use of low- cost on-line system-level error detection and correction techniques, which are tailored to the signal processing algorithms being executed on these architectures. Novel encoding schemes for various classes of signal processing algorithms are being explored. The effects of mapping large problems on limited processor mesh-connected architectures are being investigated from the viewpoint of algorithm-based checking. The effects of finite precision arithmetic on system level encodings are being studied. The fault coverage and reliability improvements due to algorithm-based checking schemes are being investigated using analytical techniques as well as functional simulations. Eventually, the research should result in the identification of some basic principles for the design of algorithm-based fault tolerance techniques.
