This research focuses on the high-level design of a high-speed Prolog computer architecture. This Prolog machine makes use of potential unification, AND, and OR parallelism in executing a Prolog program. It also employs hardware parallel units such as associative memory, multiport registers and stacks, and pipeline organization to enhance execution speed. The significance of this machine is in its very high-logic inference speed and its uniqueness in employing large-capacity associative memory as the data base. This hierarchical design is employing a software level and RTL-level design using simulation at each level.
