The object of this research is to design and implement a hardware specification language that has a hierarchical structure and a formal semantics for specifications which not only assists in automating several costly and error-prone tasks of VLSI design, but also guides test case generation. The language must have sufficient expressive power so that it can express behavioral, structural and temporal attributes of the chip or system design. The basis for the language is a purely functional specification language, developed in his doctoral research, called the Structural and Behavioral Language (SBL). The proposed research will address questions of: (1) specification of timing protocols; (2) characterization of the formal semantics; (3) implementation of the language using object-oriented programming techniques; and (4) design automation capabilities including test generation techniques. He will exercise the language by specifying a large and functionally complex VLSI chip. As we enter an era in which fabrication of several million transistors on a single silicon chip is possible, integrated circuit designers are faced with the difficult problem of specifying the external behavior of modules, their timing, and then verifying that the design meets the specifications. Unfortunately the advances in technologies have rendered existing hardware specification languages inadequate for design of large, complex VLSI circuits. They have major short-comings such as lack of high-level abstraction mechanisms, lack of formal semantic definitions, poor support for design automation, and inability to specify complex timing protocols. What is needed is research on means to express circuit design specifications that can uniformly characterize the behavior as well as timing of modules ranging in size from simple VLSI library modules to entire micro-computer systems. The proposer will attack this problem by designing a VLSI specification language which has a formal notation which will capture design decisions precisely at all stages in the design of a chip or system. This will facilitate a free exchange of design information, as well as provide the structure for automatic verification of designs. This research will lead to improvements in the quality, performance, and cost of VLSI circuit designs. This two-year award is being made under the Engineering Initiation Awards Program.
