The aim of this research is to investigate the role and form that error control should take in the design of future random access memory (RAM) systems. A system-wide hierarchic approach to the problem is being pursued. Both on-chip and board-level error control are being explored with a focus on assessing the effectiveness of each in controlling various error sources and the impact each layer has on the other. The research includes (1) Coding Techniques: construction of error-control codes with qualities suited for RAM protection; (2) VLSI Architectures: the design and fabrication of VLSI circuits that implement these codes; and (3) Performance Analysis: mathematical analysis of the effectiveness of these codes and the complexity of their implementation. The end result of the research will be a better understanding of how to construct computer memories that are larger, faster and more reliable than those being designed today. It will demonstrate how error control can be used to keep the reliability of RAM systems high even as chip feature sizes shrink and multi-megabit chips become common. This research is a collaborative effort with Dr. Chris Heegard of Cornell University
