The focus of Dr. Banerjee's work is VLSI CAD tools which run on a class of message-passing architectures, such as hypercubes. In this research he will investigate algorithms for tools which perform the task of circuit extraction from VLSI mask layouts. The technical approach is to flatten the hierarchical description into a mask description consisting of rectangles, and perform the extraction at this level. The new multiprocessor algorithms will be used for speedup and accurate, fast-circuit extraction. The algorithms will use region queries in parallel on a data structure distributed over the parallel processor. It is anticipated that this procedure will avoid the boundary effect problems that may arise when splitting a VLSI layout area into regions.
