This is a group effort involving researchers at the University of Colorado, Boulder (Gary Hachtel and M. Lightner), at the University of California, Berkeley (R. K. Brayton, A. R. Newton and A. Sangiovanni-Vincentelli), and at Stanford University (G. De Micheli). The long-range goal is understanding the theoretical structure needed for optimization of VLSI (very large scale integrated) design parameters in novel (application- specific) applications. The approach is to explore unified and systematic methods for both combination and sequential logic synthesis and minimization, which includes research on behavioral and structural synthesis tasks at higher levels of abstraction. Specific objectives are: (1) performance oriented synthesis (e.g. optimizing the delay/area tradeoff); (2) maximization of testability; and (3) extension of size capability to VLSI-sized problems. A comprehensive set of theorems, algorithms, mathematical models and their corresponding intermediate forms, and software tools will be developed. Central to the effort is utilization of their research paradigm involving a consistent mathematical treatment, optimization-based graph algorithms, and optimized mapping from one level of abstraction to the next.
