The development of area efficient fault-tolerant wafer-scale integration architectures for very high performance processor arrays that specifically ensure short and bounded interconnection lengths following restructuring is being carried out. New yield and performance models to realistically evaluate the designs are being developed. Semiconductor chips for matrix multiplication are being implemented through the MOSIS (Metal Oxide Semiconductor Implementation System) facility. Performance approaching one billion floating point operations is expected. Wafer-scale integration allows processors of high performance to be developed. In such designs, interprocessor signals are not subject to off-chip propagation delays. Issues on fault tolerance are especially important in such designs in order to overcome long delays caused by reconfiguration due to fabrication defects.
