This research is to understand, through simulation and experimental studies, the failure mechanisms of new high-density and high-speed memory technologies such as silicon DRAM's (dynamic random-access memory) with trench-type cell capacitor, GaAs (Gallium Arsenide) HEMT (High-Electron Mobility Transistor) SRAM's (static random-access memory) and CMOS (complementary metal oxide semiconductor) neural network associative memories. Based in this fault characterization, Dr. Mazumder proposes to develop appropriate test methodologies. His research is in three phases. The first phase investigates a new on-chip double-error correction circuit for the multi-megabit Silicon DRAM. This circuit will correct double-bit/word-line soft errors that cannot be corrected by conventional error correcting circuits. In the second phase, he is developing a comprehensive fault model and efficient parametric test algorithms for high-speed GaAs HEMT Static RAM; and is investigating built-in self-test circuits to generate the algorithms. The third problem is how to test neural network associative memories and a study of error correction capabilities of such memories in the presence of faulty components and erroneous input data.
